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? semiconductor components industries, llc, 2001 november, 2001 rev. 0 1 publication order number: 74alvch16245/d 74alvch16245 low-voltage 16-bit transceiver with bus hold 1.8/2.5/3.3 v (3state, noninverting) the 74alvch16245 is an advanced performance, noninverting 16bit transceiver. it is designed for very highspeed, very lowpower operation in 1.8 v, 2.5 v or 3.3 v systems. the 74alvch16245 is designed with byte control. it can be operated as two separate octals, or with the controls tied together, as a 16bit wide function. the transmit/receive (t/r n) inputs determine the direction of data flow through the bidirectional transceiver. transmit (activehigh) enables data from a ports to b ports; receive (activelow) enables data from b to a ports. the output enable inputs (oen ), when high, disable both a and b ports by placing them in a high z condition. the data inputs include active bushold circuitry, eliminating the need for external pullup resistors to hold unused or floating inputs at a valid logic state. ? designed for low voltage operation: v cc = 1.65 3.6 v ? 3.6 v tolerant inputs and outputs ? high speed operation: 2.5 ns max for 3.0 to 3.6 v 3.0 ns max for 2.3 to 2.7 v 6.0 ns max for 1.65 to 1.95 v ? static drive: 24 ma drive at 3.0 v 18 ma drive at 2.3 v 6 ma drive at 1.65 v ? supports live insertion and withdrawal ? includes active bushold to hold unused or floating inputs at a valid logic state ? i off specification guarantees high impedance when v cc = 0 v 2 ? near zero static supply current in all three logic states (20 m a) substantially reduces system power requirements ? latchup performance exceeds 250 ma @ 125 c ? esd performance: human body model >2000 v; machine model >200 v ? second source to industry standard 74alvch16245 2to ensure the outputs activate in the 3state condition, the output enable pins should be connected to v cc through a pullup resistor. the value of the resistor is determined by the current sinking capability of the output connected to the oe pin. http://onsemi.com marking diagram a = assembly location wl = wafer lot yy = year ww = work week tssop48 dt suffix case 1201 1 48 74alvch16245dt awlyyww 1 48 device package shipping ordering information 74alvch16245dt tssop 39 units/rail 74alvch16245dtr tssop 2500/tape & reel
74alvch16245 http://onsemi.com 2 figure 1. 48lead pinout (top view) figure 2. logic diagram t/r 1 a0:7 b0:7 one of eight 48 1 oe1 t/r 1 47 2 a0 b0 46 3 a1 b1 45 4 gnd gnd 44 5 a2 b2 43 6a3 b3 42 7 v cc v cc 41 8 a4 b4 40 9 a5 b5 39 10 gnd gnd 38 11 a6 b6 37 12 a7 b7 36 13 a8 b8 35 14 a9 b9 34 15 gnd gnd 33 16 a10 b10 32 17 a11 b11 31 18 v cc v cc 30 19 a12 b12 29 20 a13 b13 28 21 gnd gnd 27 22 a14 b14 26 23 a15 b15 25 24 oe2 t/r 2 oe1 t/r 2 a8:15 b8:15 oe2 1 48 24 25 1 48 25 24 a0 47 a1 46 a2 44 a3 43 b0 2 en1 t/r1 oe1 oe2 t/r2 b1 3 b2 5 b3 6 en2 en3 en4 a4 41 a5 40 a6 38 a7 37 b4 8 b5 9 b6 11 b7 12 a8 36 a9 35 a10 33 a11 32 b8 13 b9 14 b10 16 b11 17 a12 30 a13 29 a14 27 a15 26 b12 19 b13 20 b14 22 b15 23 1 ? 2 ? 3 ? 4 ? 1 1 1 1 pin names function output enable inputs transmit/receive inputs side a inputs or 3state outputs side b inputs or 3state outputs pins oen t/r n a0a15 b0b15 figure 3. iec logic diagram inputs otpts inputs otpts oe1 t/r 1 outputs oe2 t/r 2 outputs l l bus b0:7 data to bus a0:7 l l bus b8:15 data to bus a8:15 l h bus a0:7 data to bus b0:7 l h bus a8:15 data to bus b8:15 h x high z state on a0:7, b0:7 h x high z state on a8:15, b8:15 h = high voltage level; l = low voltage level; x = high or low voltage level and transitions are acceptable
74alvch16245 http://onsemi.com 3 maximum ratings (note 1) symbol parameter value unit v cc dc supply voltage 0.5 to 4.6 v v i dc input voltage 0.5 to 4.6 v v o dc output voltage 0.5 to 4.6 v i ik dc input diode current v i < gnd 50 ma i ok dc output diode current v o < gnd 50 ma i o dc output sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance (note 2) 90 c/w msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% 35% ul94vo (0.125 in) v esd esd withstand voltage human body model (note 3) machine model (note 4) charged device model (note 5) 2000 200 n/a v i latchup latchup performance above v cc and below gnd at 85 c (note 6) 250 ma maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximumrated conditions is not implied. functional operation should be restricted to the recommended operating conditions. 1. i o absolute maximum rating must be observed. 2. measured with minimum pad spacing on an fr4 board, using 10 mmby1 inch, 2ounce copper trace with no air flow. 3. tested to eia/jesd22a114a. 4. tested to eia/jesd22a115a. 5. tested to jesd22c101a. 6. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit v cc supply voltage operating data retention only 2.3 1.5 3.6 3.6 v v i input voltage (note 7) 0 3.6 v v o output voltage (high or low state) 0 3.6 v t a operating freeair temperature 40 85 c t/ v input transition rise or fall rate v cc = 2.5 v 0.2 v v cc = 3.0 v 0.3 v v cc = 5.0 v 0.5 v 0 0 0 20 10 5 ns/v 7. unused inputs may not be left open. all inputs must be tied to a highlogic voltage level or a lowlogic input voltage level.
74alvch16245 http://onsemi.com 4 dc electrical characteristics t a = 40 c to 85 c symbol parameter condition min max unit v ih high level input voltage () 1.65 v v cc 2.3 v 0.65 v cc v (note 8) 2.3 v v cc 2.7 v 1.7 2.7 v v cc 3.6 v 2.0 v il low level input voltage () 1.65 v v cc 2.3 v 0.35 v cc v (note 8) 2.3 v v cc 2.7 v 0.7 2.7 v v cc 3.6 v 0.8 v oh high level output voltage 1.65 v v cc 3.6 v; i oh = 100 a v cc 0.2 v v cc = 1.65 v; i oh = 4 ma 1.20 v cc = 2.3 v; i oh = 6 ma 2.0 v cc = 2.3 v; i oh = 12 ma 1.7 v cc = 2.7 v; i oh = 12 ma 2.2 v cc = 3.0 v; i oh = 12 ma 2.4 v cc = 3.0 v; i oh = 24 ma 2.0 v ol low level output voltage 1.65 v v cc 3.6 v; i ol = 100 a 0.2 v v cc = 1.65 v; i ol = 4 ma 0.45 v cc = 2.3 v; i ol = 6 ma 0.4 v cc = 2.3 v; i ol = 12 ma 0.7 v cc = 2.7 v; i ol = 12 ma 0.4 v cc = 3.0 v; i ol = 24 ma 0.55 v ol low level output voltage v cc = 3.6 v; v i = 0 to 3.6 v 500 a i i input leakage current 1.65 v v cc 3.6 v; 0 v v i 3.6 v 5.0 a i i(hold) minimum bushold input current v cc = 3.0 v, v in = 0.8 v 75 a current v cc = 3.0 v, v in = 2.0 v 75 v cc = 2.3 v, v in = 0.7 v 45 v cc = 2.3 v, v in = 1.7 v 45 v cc = 1.65 v, v in = 0.58 v 25 v cc = 1.65 v, v in = 1.07 v 25 i oz 3state output current 1.65 v v cc 3.6 v; 0 v v o 3.6 v; v i = v ih or v il 10 a i off poweroff leakage current v cc = 0 v; v i or v o = 3.6 v 10 a i cc quiescent supply current (n ) 1.65 v v cc 3.6 v; v i = gnd or v cc 40 a (note 9) 1.65 v v cc 3.6 v; 3.6 v v i , v o 3.6 v 40 i cc increase in i cc per input 2.7 v v cc 3.6 v; v ih = v cc 0.6 v 750 a 8. these values of v i are used to test dc electrical characteristics only. 9. outputs disabled or 3state only.
74alvch16245 http://onsemi.com 5 ac characteristics (note 10; t r = t f = 2.0ns; c l = 30pf; r l = 500 w ) limits t a = 40 c to +85 c v cc = 3.0 v to 3.6 v v cc = 2.3 v to 2.7 v v cc = 1.65 v to1.95 v symbol parameter waveform min max min max min max unit t plh t phl propagation delay input to output 1 0.5 0.5 2.5 2.5 0.5 0.5 3.0 3.0 0.5 0.5 6.0 6.0 ns t pzh t pzl output enable time to high and low level 2 0.5 0.5 3.8 3.8 0.5 0.5 4.9 4.9 0.5 0.5 9.3 9.3 ns t phz t plz output disable time from high and low level 2 0.5 0.5 3.7 3.7 0.5 0.5 4.2 4.2 0.5 0.5 7.6 7.6 ns t oshl t oslh outputtooutput skew (note 11) 0.5 0.5 0.5 0.5 0.75 0.75 ns 10. for c l = 50 pf, add approximately 300 ps to the ac maximum specification. 11. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same d evice. the specification applies to any outputs switching in the same direction, either hightolow (t oshl ) or lowtohigh (t oslh ); parameter guaranteed by design. capacitive characteristics symbol parameter condition typical unit c in input capacitance note 12 6 pf c out output capacitance note 12 7 pf c pd power dissipation capacitance note 12, 10mhz 20 pf 12. v cc = 1.8, 2.5 or 3.3 v; v i = 0 v or v cc . waveform 1 - propagation delays t r = t f = 2.0 ns, 10% to 90%; f = 1 mhz; t w = 500 ns v ih 0 v v oh v ol an, bn bn, an t phl t plh waveform 2 - output enable and disable times t r = t f = 2.0 ns, 10% to 90%; f = 1 mhz; t w = 500 ns v ih 0 v 0 v oen , t/r n an, bn t pzh v cc t phz t pzl t plz an, bn vm vm vm vm vm vm figure 4. ac waveforms vm v oh vy vx v ol vm
74alvch16245 http://onsemi.com 6 v cc symbol 3.3 v 0.3 v 2.5 v 0.2 v 1.8 v 0.15 v v ih 2.7 v v cc v cc v m 1.5 v v cc /2 v cc /2 v x v ol + 0.3 v v ol + 0.15 v v ol + 0.15 v v y v oh 0.3 v v oh 0.15 v v oh 0.15 v open pulse generator r t dut v cc r l r l c l 6 v or v cc 2 gnd test switch t plh , t phl open t pzl , t plz 6 v at v cc = 3.3 0.3 v; v cc 2 at v cc = 2.5 0.2 v; 1.8 v 0.15 v t pzh , t phz gnd c l = 50 pf for v cc = 3.0 0.3 v r l = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) figure 5. test circuit ac characteristics (t r = t f = 2.0 ns; c l = 50 pf; r l = 500 w ) limits t a = 40 c to +85 c v cc = 3.0 v t o 3.6 v v cc = 2.7 v symbol parameter waveform min max min max unit t plh t phl propagation delay input to output 3 1.0 1.0 3.0 3.0 3.6 3.6 ns t pzh t pzl output enable time to high and low level 4 1.0 1.0 4.4 4.4 5.4 5.4 ns t phz t plz output disable time from high and low level 4 1.0 1.0 4.1 4.1 4.6 4.6 ns t oshl t oslh outputtooutput skew (note 13) 0.5 0.5 0.5 0.5 ns 13. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same d evice. the specification applies to any outputs switching in the same direction, either hightolow (t oshl ) or lowtohigh (t oslh ); parameter guaranteed by design.
74alvch16245 http://onsemi.com 7 figure 6. carrier tape specifications d 1 for components 10 pitches cumulative tolerance on tape 0.2 mm ( 0.008") 2.0 mm 1.2 mm and larger center lines of cavity embossment user direction of feed k 0 see note 2 p 0 p 2 d e f w b 0 + + + k t b 1 top cover tape p see note 2 a 0 for machine reference only including draft and radii concentric around b 0 r min tape and components shall pass around radius r" without damage bending radius *top cover tape thickness (t 1 ) 0.10 mm (0.004") max embossed carrier embossment typical component cavity center line typical component center line maximum component rotation 10 camber (top view) allowable camber to be 1 mm/100 mm nonaccumulative over 250 mm 100 mm (3.937") 1 mm (0.039") max 250 mm (9.843") 1 mm max tape embossed carrier dimensions (see notes 14 and 15) tape size b 1 max d d 1 e f k p p 0 p 2 r t w 24mm 20.1mm (0.791") 1.5 + 0.1mm -0.0 (0.059 +0.004" -0.0) 1.5mm min (0.060") 1.75 0.1 mm (0.069 0.004") 11.5 0.10 mm (0.453 0.004") 11.9 mm max (0.468") 16.0 0.1 mm (0.63 0.004") 4.0 0.1 mm (0.157 0.004") 2.0 0.1 mm (0.079 0.004") 30 mm (1.18") 0.6 mm (0.024") 24.3 mm (0.957") 14. metric dimensions governenglish are in parentheses for reference only. 15. a 0 , b 0 , and k 0 are determined by component size. the clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. the component cannot rotate more than 10 within the determined cavity.
74alvch16245 http://onsemi.com 8 figure 7. reel dimensions 13.0 mm 0.2 mm (0.512" 0.008") 1.5 mm min (0.06") 50 mm min (1.969") 20.2 mm min (0.795") full radius t max g a reel dimensions tape size a max g t max 24 mm 360 mm (14.173") 24.4 mm + 2.0 mm, -0.0 (0.961" + 0.078", -0.00) 30.4 mm (1.197") figure 8. reel winding direction direction of feed barcode label hole pocket
74alvch16245 http://onsemi.com 9 tape trailer (connected to reel hub) no components 160 mm min tape leader no components 400 mm min components direction of feed cavity tape top tape figure 9. tape ends for finished goods figure 10. reel configuration user direction of feed l figure 11. package footprint f k g 48 leads
74alvch16245 http://onsemi.com 10 package dimensions tssop dt suffix case 120101 issue a ??? ??? ??? s u m 0.12 (0.005) v s t s u m 0.254 (0.010) t v b a l k u 48x ref pin 1 ident. 124 25 48 0.076 (0.003) seating d t plane dim min max min max inches millimeters a 12.40 12.60 0.488 0.496 b 6.00 6.20 0.236 0.244 c --- 1.10 --- 0.043 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.50 bsc 0.0197 bsc h 0.37 --- 0.015 --- j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.17 0.27 0.007 0.011 k1 0.17 0.23 0.007 0.009 l 7.95 8.25 0.313 0.325 m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 5. terminal numbers are shown for reference only. 6. dimensions a and b are to be determined at datum plane -w-. c g h w detail e j k1 k j1 section nn m 0.25 (0.010) f detail e n n
74alvch16245 http://onsemi.com 11 notes
74alvch16245 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. 74alvch16245/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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